基于FPGA的脉动阵列（Output Stationary）

单个PE的代码

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/02/10 19:09:28
// Design Name: 
// Module Name: systolic_pe
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module systolic_pe
#(parameter DATA_WIDTH = 16)
(
input clk,
input [DATA_WIDTH-1:0]A_shift_in,
input [DATA_WIDTH-1:0]B_shift_in,
input clear,                       //clear,set psum=0
input calc_en,                     
output [DATA_WIDTH-1:0]A_out,
output [DATA_WIDTH-1:0]B_out,
output [2*DATA_WIDTH-1:0]Sum
    );
logic [DATA_WIDTH-1:0] A;
logic [DATA_WIDTH-1:0] B;
logic [2*DATA_WIDTH-1:0] Psum;

assign A_out=A;
assign B_out=B;
//Psum
always_ff@(posedge clk)
begin
    if(calc_en)
        if(clear)
            Psum